1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to apparatus and methods for setting a mode in a semiconductor integrated circuit to adapt to errors.
2. Related Art
A DLL (delay locked loop) circuit provided in a conventional semiconductor integrated circuit is used to provide an internal clock having a phase that leads the phase of a reference clock obtained by buffering an external clock by a predetermined amount of time. When an internal clock used in the semiconductor integrated circuit is delayed by a clock buffer and a transmission line, a phase difference between the external clock and the internal clock occurs, which increases the data access time. The DLL circuit is used to solve this problem. The DLL circuit controls the phase of the internal clock to lead the phase of the external clock by a predetermined amount of time, in order to widen the effective data output period.
A conventional DLL circuit includes a replica delay for modeling the output delay of an internal reference clock, thereby generating a feedback clock. The DLL circuit compares the phase of the reference clock with the phase of the feedback clock, and generates a signal based on the result of the comparison. A delay line gives the reference clock a predetermined delay time to synchronize the phase of the reference clock with the phase of the feedback clock.
In this case, for example, a coarse locking mode or a fine locking mode is used as a method of giving the reference clock a delay time and locking the clock. In the coarse locking mode, the delay time is given by each of the unit delays provided in the delay line. In the fine locking mode, a phase mixer, not the unit delay, is used to delay the clock by a minute amount of time. The DLL circuit includes an operation mode setting apparatus in order to perform these operations. The operation mode setting apparatus receives a phase comparison signal from a phase comparator that compares the phase of the reference clock with the phase of the feedback clock, and outputs a locking completion signal for indicating the end timing of the coarse locking mode, thereby controlling an operation mode of the delay line.
The operation mode setting apparatus initializes the locking completion signal in response to a reset signal. Then, a latch circuit in the operation mode setting apparatus maintains the level of the locking completion signal that is generated in response to the phase comparison signal. Only when the reset signal is enabled, can the locking completion signal be initialized. However, the reset signal is enabled only when the DLL circuit is at an initial stage. Therefore, the state of the locking completion signal cannot be changed after it is initialized.
Actually, the toggle timing of the clock input to the DLL circuit may vary due to various factors, such as external jitter. In addition, the phase difference between the internal reference clock and the feedback clock may not decrease in the DLL circuit due to variations in PVT (process, voltage, and temperature). In this case, the DLL circuit needs to reset the delay value given to the delay line, thereby controlling the phase of the internal clock. However, since the level of the locking completion signal is maintained after the locking completion signal is enabled; it is difficult to perform the coarse locking mode again. Accordingly, the DLL circuit can perform only the fine locking mode to control the phase of the internal clock. If the phase difference between the reference clock and the feedback clock increases, it requires a lot of time to match the phases of the clock signals through the fine locking mode. In this case, a state of the duty ratio of the clock is worse, which may lead to errors in the output data.
As described above, in a conventional operation mode setting apparatus, the DLL circuit has been designed without considering the effect of external jitter or variations in PVT. Therefore, a conventional operation mode setting apparatus has problems in that it can be initialized only at the beginning of the operation of the DLL circuit and it does not support the operation mode when the operation of the DLL circuit needs to be reset due to a variation in the state of the clock. That is, a conventional operation mode setting apparatus has low adaptability to errors, such as the variation in the state of the clock, and the errors may affect the delay locking operation of the DLL circuit and the data output operation of the semiconductor integrated circuit.